To date, modern power semiconductor devices, including devices such as power MOSFETs and Insulated Gate Bipolar Transistors (IGBT), have been typically fabricated with silicon (Si) semiconductor materials. More recently, silicon carbide (SiC) power devices have been researched due to their superior properties. III-Nitride (III-N) semiconductor devices are now emerging as an attractive candidate to carry large currents and support high voltages, and provide very low on resistance, high voltage device operation, and fast switching times. A typical III-N high electron mobility transistor (HEMT), shown in FIG. 1, comprises a substrate 10, a channel layer 11, such as a layer of GaN, atop the substrate, and a barrier layer 12, such as a layer of AlxGa1-xN, atop the channel layer. A two-dimensional electron gas (2DEG) channel 19 is induced in the channel layer 11 near the interface between the channel layer 11 and the barrier layer 12. Source and drain electrodes 14 and 15, respectively, form ohmic contacts to the 2DEG channel. Gate 16 modulates the portion of the 2DEG in the gate region, i.e., directly beneath gate 16.
Field plates are commonly used in III-N devices to shape the electric field in the high-field region of the device in such a way that reduces the peak electric field and increases the device breakdown voltage, thereby allowing for higher voltage operation. An example of a field plated III-N HEMT is shown in FIG. 2. In addition to the layers included in the device of FIG. 1, the device in FIG. 2 includes a field plate 18 which is connected to gate 16, and an insulator layer 13, such as a layer of SiN, is between the field plate and the barrier layer 12. Field plate 18 can include or be formed of the same material as gate 16. Insulator layer 13 can act as a surface passivation layer, preventing or suppressing voltage fluctuations at the surface of the III-N material adjacent to insulator layer 13.
Slant field plates have been shown to be particularly effective in reducing the peak electric field and increasing the breakdown voltage in III-N devices. A III-N device similar to that of FIG. 2, but with a slant field plate 28 is shown in FIG. 3. In this device, gate 16 and slant field plate 28 are formed of a single electrode 29. Insulator layer 23, which can be of SiN, contains a recess which defines at least in part the shape of electrode 29. Herein, insulator layer 23 will be referred to as “electrode defining layer 23”. Electrode defining layer 23 can also act as a surface passivation layer, preventing or suppressing voltage fluctuations at the surface of the III-N material adjacent to electrode defining layer 23. The gate 16 and slant field plate 28 in this device can be formed by first depositing electrode defining layer 23 over the entire surface of barrier layer 12, then etching a recess through the electrode defining layer 23 in the region containing gate 16, and finally depositing electrode 29 at least in the recess.
In many applications in which III-N devices are used, for example high power and high voltage applications, it can be advantageous to include a gate insulator between gate 16 and the underlying III-N layers in order to prevent gate leakage. A device with a slant field plate and a gate insulator is shown in FIG. 4. This device can be achieved by a slight modification to the process for the device in FIG. 3. For the device in FIG. 4, the recess in electrode defining layer 23 is only etched part way through the layer (rather than all the way through the layer), after which electrode 29 is deposited. In this device, the portion of electrode defining layer 23 which is between gate 16 and the underlying III-N layers serves as a gate insulator.